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RM0008
Figure 32. Dual ADC block diagram (1)
Regular
Analog-to-digital converter (ADC)
Regular data register
(16
(12 bits)
Injected data registers
(4 x 16 bits)
channels
ADC2 (Slave)
injected
channels
internal triggers
Regular data register
(16 bits) (2)
Injected data registers
(4 x 16 bits)
ADCx_IN0
ADCx_IN1
GPIO
Ports
Regular
channels
Injected
channels
ADCx_IN15
EXTI_11
EXTI_15
Temp. sensor
V REFINT
Start trigger mux
(regular group)
Start trigger mux
(injected group)
Dual mode
control
ADC1 (Master)
1.
2.
External triggers are present on ADC2 but are not shown for the purposes of this diagram.
In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over
the entire 32 bits.
Doc ID 13902 Rev 9
211/995
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